Electrode structure and substrate processing apparatus

ABSTRACT

An electrode structure capable of adequately increasing an electron density in a processing space at a part facing a circumferential edge portion of a substrate. In a processing chamber of a substrate processing apparatus that performs RIE processing on a wafer, an upper electrode of the electrode structure is disposed to face the wafer placed on a susceptor inside the processing chamber. The upper electrode includes an inner electrode facing a central portion of the wafer and an outer electrode facing the circumferential edge portion of the wafer. The inner and outer electrodes are connected with first and second DC power sources, respectively. The outer electrode has its first secondary electron emission surface extending parallel to the wafer and its second secondary electron emission surface obliquely extending relative to the first secondary electron emission surface.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an electrode structure and a substrateprocessing apparatus, and more particularly, to an electrode structuredisposed inside a processing chamber of a substrate processing apparatusand connected to a DC power source.

2. Description of the Related Art

A substrate processing apparatus for performing plasma processing onsubstrates, e.g., wafers, includes a processing chamber in which a waferis housed, a mounting table which is disposed inside the processingchamber and on which the wafer is mounted, a shower head that supplies aprocessing gas to a processing space inside the processing chamber. Themounting table is connected with a high-frequency power supply andapplies high-frequency electric power to the processing space. Theprocessing gas supplied to the processing space is excited by thehigh-frequency electric power, whereby a plasma (cations and electrons)is produced.

Since a plasma distribution in the processing space greatly affects onresults of plasma processing on wafers, it is preferable to positivelycontrol the plasma distribution. To control the plasma distribution,especially, electron density distribution, a DC voltage is applied tothe shower head.

For application of the DC voltage to the shower head, a DC power sourceis connected to a circular disk-shaped ceiling electrode plate, which isa component part of the shower head and exposed to the processing space.When applied with a negative DC voltage, the shower head only drawscations in the plasma. Since a DC voltage has an electric potentialremaining constant with elapse of time unlike a high frequency voltage,cations are continuously drawn into the shower head. The cations drawninto the shower head cause secondary electrons to be emitted fromconstituent atoms of the shower head. As a result, the electron densityin the processing space increases at a part facing the shower head (see,for example, US Patent Application Publication No. 20060066247A1(corresponding to Japanese Laid-open Patent Publication No.2006-270019)).

The electron density distribution sometimes becomes ununiform due toaffections of the shape of the processing chamber, etc. In the case ofthe ceiling electrode plate comprised of a single electricallyconductive plate, even when a DC voltage is applied to the ceilingelectrode plate, the electron density in the processing space increasesat all the parts corresponding to the shower head, making it impossibleto eliminate the problem of uneven electron density distribution. As aresult, the electron density in the processing space decreases at a partfacing a circumferential edge portion of a wafer, posing a problem thatthe etching rate in etching processing decreases at the circumferentialedge portion of the wafer as compared to that at a central portionthereof.

SUMMARY OF THE INVENTION

The present invention provides an electrode structure and a substrateprocessing apparatus, which are capable of adequately increasing anelectron density in a processing space at a part facing acircumferential edge portion of a substrate.

According to a first aspect of this invention, there is provided anelectrode structure disposed inside a processing chamber of a substrateprocessing apparatus for performing plasma processing on a substrate, soas to face the substrate placed on a mounting table in the processingchamber, which comprises an inner electrode disposed to face a centralportion of the substrate, and an outer electrode disposed to face acircumferential edge portion of the substrate, wherein the innerelectrode is connected to a first DC power source, the outer electrodeis connected to a second DC power source, and the outer electrode has afirst surface thereof extending parallel to the substrate and a secondsurface thereof obliquely extending relative to the first surface of theouter electrode.

With the electrode structure of this invention, the outer electrodefacing a circumferential edge portion of a substrate is connected withthe second DC power source and applied with a DC voltage. When appliedwith the DC voltage, the outer electrode draws cations in a plasma andemits secondary electrons. As a result, it is possible to increase anelectron density in the processing space at a part facing thecircumferential edge portion of the substrate. The outer electrode hasits first surface extending parallel to the substrate and its secondsurface obliquely extending relative to the first surface, and secondaryelectrons are emitted from the first and second surfaces. Since thesecond surface obliquely extends relative to the first surface,secondary electrons emitted from the second surface are superimposed onsecondary electrons emitted from the first surface at the part in theprocessing space facing the circumferential edge portion of thesubstrate. As a result, it is possible to adequately increase theelectron density in the processing space at the part facing thecircumferential edge portion of the substrate.

The first and second surfaces of the outer electrode can be directedtoward the circumferential edge portion of the substrate.

With this electrode structure, the first and second surfaces aredirected to the circumferential edge portion of the substrate, andtherefore, secondary electrons emitted from the first surface and thoseemitted from the second surface are superimposed on one another at apart right above the circumferential edge portion of the substrate. As aresult, it is possible to reliably and adequately increase the electrondensity right above the circumferential edge portion of the substrate.

According to a second aspect of this invention, there is provided asubstrate processing apparatus including a processing chamber forhousing a substrate, a mounting table disposed inside the processingchamber and adapted to place the substrate thereon, and an electrodestructure disposed inside the processing chamber so as to face thesubstrate placed on the mounting table, the substrate processing beingadapted to perform plasma processing on the substrate, wherein theelectrode structure includes an inner electrode thereof disposed to facea central portion of the substrate and an outer electrode thereofdisposed to face a circumferential edge portion of the substrate, theinner electrode is connected to a first DC power source and the outerelectrode is connected to a second DC power source, and the outerelectrode has a first surface thereof extending parallel to thesubstrate and a second surface thereof obliquely extending relative tothe first surface of the outer electrode.

With the substrate processing apparatus of this invention, secondaryelectrons emitted from the second surface of the outer electrode aresuperimposed on the secondary electrons emitted from the first surfaceof the outer electrode at a part in the processing space facing acircumferential edge portion of a substrate, making it possible toadequately increase the electron density in the processing space at thepart facing the circumferential edge portion of the substrate.

Further features of the present invention will become apparent from thefollowing description of an exemplary embodiment with reference to theattached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a section view schematically showing the construction of asubstrate processing apparatus according to one embodiment of thisinvention;

FIG. 2 is a fragmentary enlarged section view schematically showing theconstruction of and around an outer electrode of an upper electrodeshown in FIG. 1;

FIG. 3 is a graph showing a relation between outer electrode surfacearea and etching rate at a circumferential edge portion of a wafer;

FIG. 4 is a graph showing the rate of increase in etching rate observedwhen a value of DC voltage applied to the outer electrode is increased;and

FIG. 5 is a graph showing relation between outer electrode surface areaand etching rate at a circumferential edge portion of a wafer in example1 of this invention and comparative examples 1 and 2.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

The present invention will now be described in detail below withreference to the drawings showing a preferred embodiment thereof.

FIG. 1 schematically shows in cross section the construction of asubstrate processing apparatus according to one embodiment of thisinvention, and FIG. 2 schematically shows in fragmentary enlarged viewthe construction of and around an outer electrode of an upper electrodein FIG. 1. The substrate processing apparatus is adapted to perform RIE(reactive ion etching) processing on semiconductor wafers as substratesby using a plasma.

As shown in FIGS. 1 and 2, the substrate processing apparatus 10includes a cylindrical processing chamber 11 and a columnar susceptor 12disposed therein and serving as a mounting table on which is placed asemiconductor wafer (hereinafter simply referred to as wafer) W having adiameter, e.g., of 300 mm.

An exhaust passage 13 is defined by an inner side wall of the processingchamber 11 and a side surface of the susceptor 12 and functions as aflow passage through which a gas in a processing space S, describedlater, is exhausted to the outside of the processing chamber 11. Anexhaust plate (exhaust ring) 14 is disposed in the middle of the exhaustpassage 13.

The exhaust plate 14 is a plate-like member formed with a number ofthrough holes and functions as a partition plate by which the processingchamber 11 is divided into an upper part and a lower part. In the upperpart (hereinafter referred to as reaction chamber) 15 of the processingchamber 11, a plasma is generated as described later. To the lower part(hereinafter referred to as exhaust chamber (manifold)) 16 of theprocessing chamber 11 are connected exhaust pipes 17, 18 through which agas in the processing chamber 11 is exhausted. The exhaust plate 14catches or reflects the plasma generated in the reaction chamber 15 toprevent leakage of the plasma to the manifold 16.

The exhaust pipe 17 is connected to a TMP (turbo molecular pump), notshown, and the exhaust pipe 18 is connected to a DP (dry pump), notshown. These pumps vacuum and depressurize the inside of the processingchamber 11. Specifically, the DP depressurizes the inside of the chamber11 from atmospheric pressure to a medium vacuum (for example, not higherthan 1.3×10 Pa (0.1 Torr)), and the TMP cooperates with the DP todepressurize the inside of the chamber 11 to a high vacuum (for example,not higher than 1.3×10⁻³ Pa (1.0×10⁻⁵ Torr)) which is lower in pressurethan the medium vacuum. The pressure within the processing chamber 11 iscontrolled by an APC valve (not shown).

The susceptor 12 inside the processing chamber 11 is connected via afirst matcher 21 to a first high-frequency power supply 19 and alsoconnected via a second matcher 22 to a second high-frequency powersupply 20. The first high-frequency power supply 19 applieshigh-frequency electric power of a relatively high frequency, e.g., 60MHz, to the susceptor 12, and the second high-frequency power supply 20applies high-frequency electric power of a relatively low frequency,e.g., 2 MHz, to the susceptor 12. The susceptor 12 functions as a lowerelectrode that applies high-frequency power to the processing space Sdefined between the susceptor 12 and a shower head 30 described later.

An electrostatic chuck 24 made of a disk-shaped insulating member andhaving an electrostatic electrode plate 23 incorporated therein isdisposed on the susceptor 12. A wafer W is mounted on the electrostaticchuck 24 when it is placed on the susceptor 12. A DC power supply 25 iselectrically connected to the electrostatic electrode plate 23 in theelectrostatic chuck 24. When a positive DC voltage is applied to theelectrode plate 23, a negative electrical potential is generated on asurface of the wafer W on the side of the electrostatic chuck 24(hereinafter referred to as the rear surface), and a potentialdifference is produced between the electrode plate 23 and the rearsurface of the wafer W. Due to the potential difference, the wafer W isattracted to and held by the electrostatic chuck 24 through a Coulombforce or a Johnsen-Rahbek force.

An annular focus ring 26 is disposed on the susceptor 12 such as tosurround the wafer W held by the susceptor. The focus ring 26 is made ofa conductive member, e.g., silicon, and converges plasma toward thesurface of the wafer W to improve the efficiency of RIE processing.

An annular coolant unit 27 is provided inside the susceptor 12 andextends circumferentially of the susceptor. A low temperature coolant,for example, cooling water or a Galden fluid (registered trademark), issupplied from a chiller unit (not shown) via a coolant pipe 28 into thecoolant chamber 27 for circulation. The susceptor 12 is cooled by thelow temperature coolant and cools the wafer W and the focus ring 26 viathe electrostatic chuck 24.

A plurality of heat-transfer gas feed holes 29 of a gas feed pipe areopened to that part of the upper surface of the electrostatic chuck 24(hereinafter referred to as the suction surface) by which the wafer W isattracted and held. Helium (He) gas, as a heat transfer gas, is suppliedfrom the gas feed holes 29 to a gap between the suction surface of theelectrostatic chuck 24 and the rear surface of the wafer W. The heliumgas supplied to the gap efficiently transfers heat of the wafer W to theelectrostatic chuck 24.

The shower head 30 is disposed at a ceiling portion of the processingchamber 11. The shower head 30 includes an upper electrode 31 (electrodestructure) disposed to face the wafer W placed on the susceptor 12(hereinafter referred to as the placed wafer W) so as to be exposed tothe processing space S, an insulating plate 32 made of an insulativemember, and an electrode support member 33 that supports via theinsulating plate 32 the upper electrode 31 hanging therefrom. The upperelectrode 31, the insulating plate 32, and the electrode support member33 are stacked one upon another in this order.

The electrode support member 33 has a buffer chamber 39 formed therein.The buffer chamber 39 defines a columnar space, which is divided intoinner and outer buffer chambers 39 a, 39 b by an annular sealing member,e.g., an O-ring 40.

A processing gas introduction pipe 41 is connected to the inner bufferchamber 39 a, and a processing gas introduction pipe 42 is connected tothe outer buffer chamber 39 b. A processing gas is introduced into theinner buffer chamber 39 a via the gas introduction pipe 41, and aprocessing gas is introduced into the outer buffer chamber 39 b via thegas introduction pipe 42.

The processing gas introduction pipes 41, 42 each include a mass flowcontroller (MFC), not shown. Therefore, amounts of flow of processinggases introduced into the inner and outer buffer chambers 39 a, 39 b arecontrolled independently of each other. As shown in FIG. 2, the bufferchamber 39 is communicated with the processing space S via gas holes 43formed in the electrode support member 33, gas holes 33 formed in theinsulating plate 32, and gas holes 36 formed in the upper electrode 31.The processing gases introduced into the inner and outer buffer chambers39 a, 39 b are supplied to the processing space S. At that time, theamounts of flow of processing gases introduced into the inner and outerbuffer chambers 39 a, 39 b are adjusted, whereby a distribution ofprocessing gases in the processing space S is controlled.

With the substrate processing apparatus 10, when RIE processing isperformed on the placed wafer W, the shower head 30 supplies processinggases into the processing space S, the first high-frequency power supply19 applies high-frequency power of 60 MHz to the processing space S viathe susceptor 12, and the second high-frequency power supply 20 applieshigh-frequency power of 2 MHz to the susceptor 12. The processing gasesare excited by the high-frequency power of 60 MHz and converted intoplasma. The high-frequency power of 2 MHz produces a bias voltage on thesusceptor 12, and therefore cations or electrons in the plasma are drawninto the surface of the placed wafer W, whereby RIE processing isperformed on the wafer W.

To control apart of electron density distribution in a processing space,there has been developed a method in which an upper electrode is dividedinto inner and outer electrodes respectively facing a central portionand a circumferential edge portion of a wafer, and DC voltages ofnegative polarity are independently applied to the inner and outerelectrodes. In this method, a DC voltage of a value different from thatapplied to the inner electrode is applied to the outer electrode tothereby independently control the electron density in the processingspace at parts facing the outer and inner electrodes.

With regard to this method, the present inventors et al. conductedexperiments on RIE processing and had knowledge that the electrondensity in the processing space at a part facing an opposite surface ofthe outer electrode (hereinafter referred to as the part facing theouter electrode) increased with the increase in surface area of thatsurface of the outer electrode facing the processing space (hereinafterreferred to as the outer electrode surface area), resulting in increasein etching rate at a circumferential edge portion of the wafer (see FIG.3).

The present inventors et al. also had knowledge that the electrondensity at the part facing the outer electrode increased with theincrease in a value of DC voltage applied to the outer electrode,resulting in increase in etching rate at the circumferential edgeportion of the wafer. Specifically, it was confirmed that the etchingrate at the circumferential edge portion of the wafer increased by about7% when an absolute value of DC voltage applied to the outer electrodewas increased from 300 volts to 900 volts, with the DC voltage appliedto the inner electrode kept at an absolute value of 300 volts (see FIG.4).

However, in an ordinary substrate processing apparatus, there areprocessing chamber component parts around the outer electrode, whichmakes it difficult to increase the outer electrode surface area up to acertain value or more. Due to limited performance of the DC powersource, etc., it is often difficult to increase DC power applied to theouter electrode up to a certain value or more. Thus, it is usuallydifficult to adequately increase the electron density in the processingspace at a part facing the circumferential edge portion of the wafer.

In view of the above, the upper electrode 31 of the substrate processingapparatus 10 has its inner electrode 34 facing a central portion of theplaced wafer W and its outer electrode 35 arranged to surround the innerelectrode 34 and facing a circumferential edge portion of the placedwafer W, and the outer electrode 35 has a first secondary electronemission surface 35 a (first surface) thereof extending parallel to theplace wafer W and a second secondary electron emission surface 35 b(second surface) thereof obliquely extending relative to the firstsecondary electron emission surface 35 a toward the placed wafer W. Thefirst and second secondary electron emission surfaces 35 a, 35 b aredirected to the circumferential edge portion of the placed wafer W.

The inner electrode 34 is made of a circular disk shaped member having adiameter, e.g., of 300 mm, and is formed with a number of gas holes 36extending in the thickness direction of the inner electrode 34. Theouter electrode 35 is an annular member having an outer diameter, e.g.,of 380 mm and an inner diameter, e.g., of 300 mm. The inner and outerelectrodes 34, 35 are each made of a conductive or semiconductormaterial, e.g., single crystal silicon.

First and second DC power sources 37, 38 are respectively connected tothe inner and outer electrode 34, of the upper electrode 31, and DCvoltages are independently applied to the electrodes 34, 35.

During RIE processing in the substrate processing apparatus 10, negativeDC voltages are applied from the first and second DC power sources 37,38 to the inner and outer electrodes 34, 35 of the upper electrode 31.Cations in the plasma produced in the processing space S are thereforedrawn into the inner and outer electrodes 34, 35, and supply energy toelectrons of constituent atoms of the electrodes 34, 35. When thesupplied energy exceeds a certain value, electrons of constituent atomsas secondary electrons are emitted from the surface of the innerelectrode 34 and the first and second secondary electron emissionsurfaces 35 a, 35 b of the outer electrode 35.

Since the inner electrode 34 is made of a disk-shaped member asdescribed above, only that surface of the inner electrode 34 extendingparallel to the placed wafer W is exposed to the processing space S.Therefore, the secondary electrons emitted from the surface of the innerelectrode 34 are uniformly distributed from a central portion to acircumferential edge portion of the wafer W. Thus, RIE processing ispromoted on the entire surface of the placed wafer W.

As described above, both the first and second secondary electronemission surfaces 35 a, 35 b of the outer electrode 35 are directed tothe circumferential edge portion of the placed wafer W. Therefore,secondary electrons emitted from the first and second secondary electronemission surface 35 a, 35 b are superimposed on one another at locationsright above the circumferential edge portion of the place wafer W. As aresult, it is possible to adequately increase the electron density rightabove the circumferential edge portion of the placed wafer W, and RIEprocessing on the circumferential edge portion of the placed wafer W ispromoted.

Operations of component parts of the substrate processing apparatus 10are controlled by a CPU of a control unit (not shown) of the substrateprocessing apparatus 10.

With the upper electrode 31 as an electrode structure according to thisembodiment, the second DC power source 38 is connected to the outerelectrode 35 facing the circumferential edge portion of the placed waferW, and a DC voltage is applied to the outer electrode 35. When appliedwith the DC voltage, the outer electrode 35 draws cations in the plasmaand emits secondary electrons, whereby the electron density in theprocessing space S right above the circumferential edge portion of theplaced wafer W can be increased. The outer electrode 35 has its firstsecondary electron emission surface 35 a extending parallel to theplaced wafer W and its second secondary electron emission surface 35 bextending obliquely relative to the electron emission surface 35 atoward the placed wafer W, and secondary electrons are emitted from theelectron emission surfaces 35 a, 35 b. Since both the surfaces 35 a, 35b are directed to the circumferential edge portion of the placed waferW, the electron density right above the circumferential edge portion ofthe placed wafer W can adequately be increased, whereby RIE processingon the circumferential edge portion of the wafer W can be promoted.

With the upper electrode 31, the electron density right above thecircumferential edge portion of the placed wafer W can be adequatelyincreased, without the need of increasing the area of the surface of theouter electrode 35 facing the wafer W. As a result, it is possible toreduce an amount of use of high-priced single crystal silicon, making itpossible to decrease the fabrication cost of the upper electrode 31.

In the upper electrode 31, both the first and second secondary electronemission surfaces 35 a, 35 b are directed to the circumferential edgeportion of the placed wafer W. However, the second secondary electronemission surface 35 b may not be directed to the circumferential edgeportion of the placed wafer W. For example, the electron emissionsurface 35 b may extend perpendicular to the first secondary electronemission surface 35 a. Even in that case, the electron density at a partfacing the circumferential edge portion of the placed wafer W can beadequately increased since secondary electrons emitted from the electronemission surfaces 35 a, 35 are superimposed on one another in the partin the processing space S facing the circumferential edge portion of theplaced wafer W.

Furthermore, the second secondary electron emission surface 35 b may notbe a flat surface, but may be a parabolic surface directed to thecircumferential edge portion of the placed wafer W. In that case, it ispossible to emit secondary electrons from the electron emission surface35 b concentratedly toward the circumferential edge portion of theplaced wafer W, whereby the electron density right above thecircumferential edge portion of the wafer W can further be adequatelyincreased.

In the above described embodiment, the substrate subjected to etchingprocessing is a semiconductor wafer W. However, the substrate subjectedto etching processing is not limited thereto, and may be, for example, aglass substrate for a display such as LCD (liquid crystal display) orFPD (flat panel display).

EXAMPLE

Next, an example of this invention is described.

Example 1

The present inventors performed RIE processing on a placed wafer W byusing the substrate processing apparatus 10, and measured the etchingrate by the RIE processing at a circumferential edge portion of thewafer W. The result is shown by a black-circle mark in a graph of FIG.5.

Comparative Examples 1, 2

The present inventors prepared two outer electrodes each only having asurface extending parallel to a placed wafer W and having differentsurface areas, and then replaced the outer electrode 35 of the substrateprocessing apparatus 10 with one of the prepared outer electrodes.Subsequently, RIE processing was performed on the placed wafer W, andthe etching rate by the RIE processing at a circumferential edge portionof the placed wafer W was measured (Comparative Example 1). Then, theouter electrode was replaced by another outer electrode, and a similarmeasurement was made (Comparative Example 2). The results are shown byblack diamond-shaped marks in the graph of FIG. 5.

In the graph of FIG. 5, surface area of outer electrode is taken alongabscissa and etching rate is taken along ordinate. The surface area ofouter electrode in Example 1 corresponds to the total area of the firstand second secondary electron emission surfaces 35 a, 35 b of the outerelectrode 35. The surface area of outer electrode in each of ComparativeExamples 1, 2 corresponds to the area of the surface of the outerelectrode extending parallel to the placed wafer W. In the graph of FIG.5, the surface areas of the outer electrodes of and the etching rates inExample 1 and Comparative Examples 1, 2 are each represented by anumerical value which assumes a value of 1 for those of ComparativeExample 1. It is understood from the graph of FIG. 5 that, by providingthe second secondary electron emission surface 35 b extending obliquelyrelative to the first secondary electron emission surface 35 a ratherthan by increasing the surface area of outer electrode, the electrondensity right above the circumferential edge portion of the placed waferW can be efficiently and adequately increased, whereby RIE processing atthe circumferential edge portion of the placed wafer W can be promoted.

1. An electrode structure disposed inside a processing chamber of asubstrate processing apparatus for performing plasma processing on asubstrate, so as to face the substrate placed on a mounting table in theprocessing chamber, comprising: an inner electrode disposed to face acentral portion of the substrate; and an outer electrode disposed toface a circumferential edge portion of the substrate, wherein said theinner electrode is connected to a first DC power source, said outerelectrode is connected to a second DC power source, and said outerelectrode has a first surface thereof extending parallel to thesubstrate and a second surface thereof obliquely extending relative tothe first surface of said outer electrode.
 2. The electrode structureaccording to claim 1, wherein the first and second surfaces of saidouter electrode are directed toward the circumferential edge portion ofthe substrate.
 3. A substrate processing apparatus including aprocessing chamber for housing a substrate, a mounting table disposedinside the processing chamber and adapted to place the substratethereon, and an electrode structure disposed inside the processingchamber so as to face the substrate placed on the mounting table, thesubstrate processing being adapted to perform plasma processing on thesubstrate, wherein: the electrode structure includes an inner electrodethereof disposed to face a central portion of the substrate and an outerelectrode thereof disposed to face a circumferential edge portion of thesubstrate, said inner electrode is connected to a first DC power sourceand said outer electrode is connected to a second DC power source, andsaid outer electrode has a first surface thereof extending parallel tothe substrate and a second surface thereof obliquely extending relativeto the first surface of said outer electrode.
 4. The substrateprocessing apparatus according to claim 3, wherein the first and secondsurfaces of said outer electrode are directed toward the circumferentialedge portion of the substrate.